Achieving local as well as global planalization is one of the prime requirements in micro fabrication methods. Many different methods of dielectric planarization are practiced in order to achieve local and global planarity. Chemical mechanical polishing (CMP) has emerged as the planarization method of choice [Li, 2000] because of its ability to planarize over longer length scales than traditional planarization techniques and is considered to provide far better local and global planarization [Steigerwald, et al 1997, Sivaram et al 1992, Patrick et al 1991]. Besides interlayer dielectric planarization, CMP has also find applications in shallow trench isolation, damascene technologies [e.g., Kaanta 1991, Kranenberg 1998]. Despite the advantages that CMP enjoys, the process still suffers from large global non-uniformities within a die and across a wafer. FIGS. 1A and 1B show a pictorial view of a CMP machine set-up. In FIG. 1A, a top view of a table or platen 10 and its associated polishing pad with a wafer carrier 14 mounted on a rotatable axis 12. FIG. 1B illustrates a side view showing the wafer carrier and wafer 14 adjacent the polishing pad of the table 10 which is mounted on a rotatable axis 16. Machines with multiple heads are also available. In a typical dielectric polishing process, the wafer is held by a rotating carrier 14 with the active wafer surface facing the rotating polish table (platen 10). On top of the table 10 is a porous polyurethane pad on which, slurry of colloidal silica suspended in aqueous solution is poured. Slurries with different chemical compositions are used to polish metal and other films. In a typical configuration, the carrier and table rotate in the same direction but with the two rotating axes offset by some distance. The carrier also exhibits an orbital motion.
The arrangement results in relative motion between any position on the wafer and the polishing pad. The slurry chemically reacts with the wafer surface and together with the mechanical force exerted by the pad and the colloidal silica particles; the wafer surface is abraded [Cook, 1990]. The material removal also relies on the relative motion between the wafer and pad surface. The pad surface becomes glazed over time, resulting in a lower polish rate. A diamond tipped conditioner minimizes this effect by scratching the surface of the pad thus maintaining its polishing efficiency.
Although CMP can planarize over longer length scales, pattern density variation across a chip leads to large variation in global thickness across the die. CMP therefore removes local steps but generates global steps as illustrated in FIG. 2. Due to the initial pattern density difference, the two regions on a chip polish at different rates. At some time T1, local planarity is achieved in the low density area of density PD1. After some time T2, local planarity is also achieved in the high density region of initial density PD2. The initial difference in layout pattern density creates a global step height between these two regions due to the difference in removal rates before the local patterns are planarized. [Ouma, 1998] Although the global thickness variation is no longer a serious lithography concern, it still has a serious impact on subsequent process steps such as via etching. Depending on the location of the via, the depth will be different thus making it difficult to determine a suitable etch time. The global thickness variation also impacts circuit performance: long-range clock wires passing through regions of different thicknesses result in different capacitances and may result in clock skew [Stine et al 1997]. The length scale over which complete local planarity is achieved is a function of the elastic properties of the polish pad and other process conditions. This length scale is easily visualized by polishing a step density pattern. As shown in FIG. 3, away from the density boundary, local planarity is achieved.
Even though many publications have been made on the various modeling techniques in CMP to achieve global planarity, using material removal control techniques, pad property variation etc., not many concentrate on obtaining global planarity over pattern dependant surfaces. Most of them assume a uniform pattern density across the entire polish span. Eamkajornsiri et al [2001] concludes that yield improvement in CMP can be improved considerably by varying the interface pressure, wafer curvature and polishing time, in wafer scale, it doesn't taken into account the variation in pattern density across the die. Tugbawa et al [2001] proposes a contact mechanics based density step height model of pattern dependencies for predicting thickness evolution. Ouma et al [2002], provides a model using a 2 step FFT of the incoming wafer surface and an elliptic weighting function corresponding to pad deformation profile to obtain estimates of effective pattern densities across the entire wafer.
Therefore, it is a primary object, feature, or advantage of the present invention to improve over the state of the art.
It is a further object, feature, or advantage of the present invention to obtain local and global planarity in dielectric and metal planarizations in variable pattern density surfaces.
A further object, feature, or advantage of the present invention is to provide improved uniformity in step height across the die.
One or more of these and/or other objects, features, or advantages of the present invention will become apparent from the specification and claims that follow.